Semiconductor structures and ICs are manufactured using a wide variety of well-known techniques. In the manufacturing of semiconductor devices or ICs, active/passive components are formed on a semiconductor wafer or chip, and then interconnected in a desired manner.
In such semiconductor structures and ICs, it is well known to form thin film resistors using either a damascene method or a subtractive etch method in the back-end-of-the-line of the semiconductor wafer or chip. The term “back-end” is used herein to denote BEOL interconnect or wiring levels. BEOL thin film resistors are typically formed inlaid or on top of a dielectric material which is in electrical communication with the underlying semiconductor chip or wafer by means of one or more conductive vias.
BEOL thin film resistors are preferred over other types of resistors because of their lower parasitics. A major drawback with such resistors is that the sheet resistivity of the various resistors formed over the entire wafer or chip may vary and, in some instances, go beyond specifications for high-performance ICs. That is, some of the BEOL resistors formed across a wafer or chip may have a sheet resistance that is beyond the tolerance of current high-performance ICs due to non-uniform thickness deposition.
In the semiconductor industry, it is important to control the tolerance of the BEOL thin film resistor because the tolerance directly affects the circuit design, speed, and manufacturability; i.e., ability to meet circuit performance specifications. To date, however, there are no satisfactory means to control the tolerance of BEOL thin film resistors. Typically, wafers are sorted to specification, and the wafers out of specification are scrapped. Hence, there is a need for providing a method which is capable of improving the tolerance of BEOL thin film resistors to yield more chips in-specification.